EEPROM's are memory devices which use floating gate metal oxide semiconductor technology to store data. Each EEPROM cell contains a floating gate MOS transitor. One logical state is written into the EEPROM cell by providing a required voltage between the source, gate and drain of the floating gate MOS transistor in order to cause tunneling of electrons from the substrate through the floating-gate insulator onto the floating gate. This charge may be stored in the floating gate for a number of years. The other logical state is written by providing specific voltages between the source, gate and drain which discharge electrons from the floating gate of the EEPROM cell by tunneling electrons through the floating gate insulator layer from the floating gate to the substrate.
FIG. 1 is a schematic diagram of a typical EEPROM cell. When memory cell 10 is addressed for reading, a positive voltage is applied to wordline 5 which causes transistors 4 and 11 to turn on. If electrons are stored on the floating gate of floating-gate transistor 12, these stored electrons raise the threshold voltage of transistor 12 above the voltage provided on row line 3. Therefore, memory cell 10 provides a high impendance between column line 7 and column line 8. Therefore, the column decoder (not shown) of the memory including memory cell 10 detects a high impedance between column leads 7 and 8 and provides an appropriate data output signal.
If no electrons are stored on the floating gate of floating gate transistor 12, the high-voltage signal provided on column line 3 causes floating gate transistor 12 to turn on. Therefore, the column decorder (not shown) detects a low impedance between column lines 7 and 8 and provides an appropriate data output signal. Transistor 13 and tunneling region 14 allow a specific tunneling voltage to be placed below the floating gate of floating gate transistor 12 which is independent of the substrate voltage.
FIG. 2 is a plan view of memory cell 10. Moat regions 22 provide the sources and drains for floating gate transistor 12, pass transistor 13 and pass transistor 11. Floating gate transistor 12 is programmed by charging floating gate 25 through the tunneling oxide in tunnel region 14. Finally, column lines 7 and 8 are connected to contacts 21 and 26 respectively. Lead 9 is provided by the extension of moat region 22 to vertically (relative to the page) adjacent cells.
FIG. 3 is a schematic side view of cut away AA of FIG. 2. Word line/gate 24 is insulated from substrate 35 by gate oxide regions 34, thus forming channel regions between moat regions 22 (FIG. 2). FIG. 4 is a schematic side-view diagram of floating gate field effect transistor 12 and tunneling region 14 which is cut away at point BB in FIG. 2. In addition to the components discussed with regard to FIGS. 2 and 3, FIG. 4 depicts inter-level oxide layer 36 and tunnel-oxide layer 37. Tunnel oxide layer 37 is approximately 100 angstroms thick and is designed to facilitate tunneling of electrons from N-type region 52 to floating gate 25.
FIGS. 5 and 6 are sideview schematic diagrams depicting cut aways CC and DD of FIG. 2.
The amount of charge tunneled to floating gate 25 is dependent upon the voltage developed across tunnel oxide 37. The voltage across tunnel oxide 37 can be determined using the laws of capacitive coupling to be described by the equation EQU C0V0=C10V1+C20V2+C30V3+C40V4+Q0 (1)
where,
C0 equals C10+C20+C30+C40, PA1 V0 is the voltage on floating gate 25, PA1 C10 is the capacitance between the floating gate 25 and substrate 35 across gate oxide 34, PA1 V1 is the voltge on substrate 35, PA1 C20 is the capacitance between floating gate 25 and N-type region 52 across tunnel oxide 37, PA1 V2 is the potential on N-type diffusion 52, PA1 C30 is the capacitive coupling between control gate 23 and floating gate 25, PA1 V3 is the potential of control gate 23, PA1 C40 is the capacitance between floating gate 25 and the substrate across field oxide regions 31, 32 and 33, PA1 V4 is the potential of substrate 35, and PA1 Q0 is equal to the net electrical charge on the floating gate.
Under typical operating conditions, V1 and V4 are approximately zero volts, thus equation 1 becomes, EQU C0V0=Q0+C20V2+C30V3 (2)
During the charging operation (i.e., creating a net negative charge on floating gate 25), V3 is typically 15V and V2 is typically 0V, thus equation 2 becomes, EQU V0=(Q0+C30V3)/ C0 (3)
Because C10 and C40 are small relative to C20 and C30, the voltage drop across tunnel oxide 37 (V0 minus V2, V2 equal to zero) is proportional to C30/ (C20+C30) with an additive factor of Q0.
During the discharging operation (i.e. creating a net positive or net zero charge), V2 is typically 15V and V3 is typically 0V and equation 2 becomes, EQU V0=(Q0+C20V2)/ C0 (4)
The discharging voltage V2-V0, which is, EQU V2-V0=((C0-C20)V2-Q)/C0=((C10+C30+C40)V2-Q)/ C0 (5)
Because C10 and C40 are small relative to C20 and C30, V2-V0 is proportional to C30/ (C20+C30) with an additive factor of Q0.
As can be seen from equations 3 and 5, the tunneling voltage increases as C30 increases. This capacitance is limited by the area of overlap between word line 23 and floating gate 25 in the prior art. Therefore, it is an object of the present invention to provide a structure whereby the capacitive coupling between the word line and the floating gate in a EEPROM memory cell may be increased without increasing the surface area of the EPROM cell.